

|
專利國別 |
美國 |
發表日期 |
2021-06-01 11:43:54 |
|
專利讓與 |
一、依據本校第320次智慧財產權審議委員會辦理。 二、公告日:2021年06月01日(星期二)。 三、公告讓與期間:自公告日起3個月。 四、敬請有興趣辦理受讓之廠商,或對受讓申請程序有任何疑問者,聯繫研發處技術推廣中心洽談,電話:05-2720411轉16501、16505。 |
||
|
本校案號 |
P100016A |
||
|
專利名稱 |
適用於低工作電壓之記憶體電路「MEMORY CIRCUIT PROPERLY WORKABLE UNDER LOW WORKING VOLTAGE」 |
||
|
發明人 |
王進賢、張倍耀 |
||
|
所屬院 |
工學院 |
提案單位 |
電機工程學系暨研究所 |
|
類型 |
發明 |
專利權人 |
國立中正大學 |
|
申請號 |
13/477,437 |
申請日期 |
2012-05-22 |
|
公開號 |
US 2013-0314977 A1 |
公開期 |
2013-11-28 |
|
證書號 |
US 8,743,592 B2 |
核准日期 |
2014-06-03 |
|
國際分類號 |
G11C-011/412(2006.01) |
||
|
專利權期間 |
2012.05.22~2032.05.22 (延長234天至2033.01.11) |
||
|
專利摘要 |
A memory circuit properly workable under low working voltage includes a plurality of write word lines, a plurality of write bit lines, a plurality of read/write word lines, a plurality of read/write bit lines, a plurality of read/write inverted word lines, a plurality of virtual voltage source circuits, a plurality of virtual ground circuits, and a plurality of asymmetrical RAM cells constituting a cell array. The asymmetrical RAM cells are formed of seven transistors, five of which are NMOS transistors and two of which are PMOS transistors. The virtual voltage power source circuit and the virtual ground circuit can reinforce the write-in and read abilities under low working voltage to make the write-in and read actions more stable, decrease leakage current, and lower power consumption. |
||
|
圖示 |
|||

