【專利公告讓與】P94010A-多重功能與可擴充性設計之視訊編碼方法及其電路系統「DESIGN TECHNIQUES AND THEIR CIRCUIT DESIGNS FOR VERSATILE AND SCALABLE VIDEO CODING」

讓與-上隔線

專利國別

  美國   

發表日期

2021-06-01 11:36:23

專利讓與

一、依據本校第320次智慧財產權審議委員會辦理。

二、公告日:2021年06月01日(星期二)。

三、公告讓與期間:自公告日起3個月。

四、敬請有興趣辦理受讓之廠商,或對受讓申請程序有任何疑問者,聯繫研發處技術推廣中心洽談,電話:05-2720411轉16501、16505。

本校案號

P94010A

專利名稱

多重功能與可擴充性設計之視訊編碼方法及其電路系統「DESIGN TECHNIQUES AND THEIR CIRCUIT DESIGNS FOR VERSATILE AND SCALABLE VIDEO CODING」

發明人

郭峻因、陳冠宏、王進賢

所屬院

工學院

提案單位

晶片系統研究中心

類型

發明

專利權人

申請號

11/472,344

申請日期

2006-06-22

公開號

US 2007-0297500 A1

公開日期

2007-12-27

證書號

US 7,724,975 B2

核准日期

2010-05-25

國際分類號

G06K-009/36(2006.01)

專利權期間

2006.06.22~2026.06.22(延長997天2029.03.15)

專利摘要

Design techniques and their circuit designs for versatile and scalcble video coding are proposed, in which the inner product operation in the transform coding expression is taken apart into a series of add and shift operations, and the expression is partitioned into several sub-expression. Taking each order of the add-and-shift series as a clock period, several adders/subtractors and a shift accumulator are used to carry out corresponding additions/subtractions and shift operations to finish the inner product operations. The calculating result is accumulated until all the orders are finished. The final accumulated value is the output of the transform coding. Data throughput rate can thus be enhanced to save the power consumption of the circuit system. Moreover, a dynamic guarded computation method and a switching power suppression technique are provided to further lower the power consumption

圖示

94010-US

讓與-下隔線