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專利國別 |
美國 |
發表日期 |
2012-09-26 14:25:42 |
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本校案號 |
P94011A |
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專利名稱 |
編譯器中省電最佳化排程之方法「POWER-AWARE COMPILING METHOD」 |
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發明人 |
張榮貴、林宗彥 |
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所屬院 |
工學院 |
提案單位 |
資訊工程學系暨研究所 |
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類型 |
發明 |
專利權人 |
國立中正大學 |
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申請號 |
012/566,697 |
申請日期 |
2006-12-05 |
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公開號 |
0 |
公開日期 |
2007-12-27 |
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證書號 |
US 8,108,850 B2 |
核准日期 |
2011-12-06 |
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國際分類號 |
G06F-009/45(2006.01) |
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專利權期間 |
2006.12.05~2026.12.05(延長1280天至2030.06.07) |
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專利摘要 |
The present invention discloses a power-aware compiling method, wherein the power model of an application program are established via building and analyzing the control flow chart and the data flow chart of the application program; each functional until of the application program is assigned a power mode; a judgment is undertaken to determine whether the idle functional units are independent; if none dependency exists between those idle function units, the program codes of the same idle function units are merged into a new basic block, and the idle function units are turned off for saving power; each new basic block is assigned an appropriate power mode; the basic blocks with the same power modes are merged to reduce the transitions between different power modes; thus, the power consumed by changing voltage or frequency can be decreased. |
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圖示 |
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