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專利國別 |
美國 |
發表日期 |
2014-08-14 10:22:25 |
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本校案號 |
P99006A |
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專利名稱 |
具解時脈扭曲之延遲鎖定電路「CLOCK DE-SKEWING DELAY LOCKED LOOP CIRCUIT」 |
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發明人 |
王進賢、鄭竣元、劉志強 |
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所屬院 |
工學院 |
提案單位 |
晶片系統研究中心 |
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類型 |
發明 |
專利權人 |
國立中正大學 |
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申請號 |
13/158,697 |
申請日期 |
2011-06-13 |
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公開號 |
US 2012-0112810 A1 |
公開日期 |
2012-05-10 |
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證書號 |
US 8,294,498 B2 |
核准日期 |
2012-10-23 |
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國際分類號 |
H03L-007/06(2006.01) |
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專利權期間 |
2011.06.13~2031.06.13 |
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專利摘要 |
A clock de-skewing delay locked loop circuit is revealed. In the clock de-skewing delay locked loop circuit, a timing control circuit generates a first and a second clock signals according to an external and an internal clock signal. A clock delay line delays the first clock signal or the external clock signal to generate delay signals. A delay mirror circuit synchronizes the internal clock signal with the external clock signal. A phase adjustment circuit inverts the internal clock signal according to the phase difference. An inverting buffer circuit buffers the external clock signal or the first clock signal for adding an initial delay time so as to make a duty cycle of internal clock signal and of the external clock signal complement each other. Thus the duty cycle of the external clock signal in the proposed circuit is not necessarily 50%. |
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圖示 |
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