專利國別

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發表日期

2012-06-22 09:31:22

本校案號

P89002A

專利名稱

低功率動態邏輯電路「LOW POWER DYNAMIC LOGIC CIRCUIT」

發明人

王進賢、張清榮、葉經緯

所屬院

工學院

提案單位

電機工程學系暨研究所

類型

發明

專利權人

國立中正大學

申請號

09/854,113

申請日期

2001-05-11

公開號

0

公開日期

2002-11-14

證書號

US 6,492,839 B2

核准日期

2002-12-10

國際分類號

H03K-019/096(2006.01)

專利權期間

2001.05.11~2021.05.10

專利摘要

A low power dynamic logic circuit. By shifting a discharge NMOS transistor of a conventional dynamic logic circuit between an output terminal and a logic block, plus an additional charge and discharge control, the operation speed and power consumption of a dynamic circuit can be effectively improved. Using the charge redistribution to speed up the circuit operation and to reduce the body effect that affects the operation speed, the speed of the novel dynamic logic circuit is enhanced. By transferring the lump capacitor of the charge/discharge, the dynamic power can be effectively reduced. The lower power dynamic logic circuit can be used independently or combined with a conventionally dynamic logic circuit.

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