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【專利核准公告】P100006A-降低電路規格並減少功率消耗之三角積分調變器合成方法「SYNTHESIS METHOD OF SIGMA-DELTA MODULATOR CAPABLE OF RELAXING CIRCUIT SPECIFICATION AND REDUCING POWER」(已終止維護)

專利核准-上隔線

專利國別

  美國   

發表日期

2014-08-14 10:03:16

本校案號

P100006A

專利名稱

降低電路規格並減少功率消耗之三角積分調變器合成方法「SYNTHESIS METHOD OF SIGMA-DELTA MODULATOR CAPABLE OF RELAXING CIRCUIT SPECIFICATION AND REDUCING POWER」

發明人

李順裕、洪家華、翁靜怡

所屬院

工學院

提案單位

晶片系統研究中心

類型

發明

專利權人

立中正大學

申請號

13/429,020

申請日期

2012-03-23

公開號

US20130050000A1

公開日期

2011-08-26

證書號

US 8,487,798 B2

核准日期

2013-07-16

國際分類號

H03M-003/00(2006.01)

專利權期間

2013.03.23~2032.03.23

專利摘要

A synthesis method of Sigma-delta modulator capable of relaxing circuit specification and reducing power consumption, comprising the following steps: firstly, set a target bandwidth and a target performance; upon obtaining a Noise Transfer Function(NTF), perform coefficient synthesis a first time, to ascertain a plurality sets of first performance results corresponding to said NTF, and obtain a plurality sets of first circuit specifications fulfilling said target performing, through analyzing circuit non-ideal effect of said first performance results. Next, increase an oversampling ratio of parameters, to obtain a plurality sets of second performance results, and a plurality sets of second circuit specifications. Then, increase quantizer bit number, and increase attenuation quantity, to obtain a plurality sets of third circuit specifications. Finally, compare said first, second and third circuit specification to select one of greatest variation to perform calibrations.

圖示

【專利核准公告】P100006A-降低電路規格並減少功率消耗之三角積分調變器合成方法「SYNTHESIS METHOD OF SIGMA-DELTA MODULATOR CAPABLE OF RELAXING CIRCUIT SPECIFICATION AND REDUCING POWER」

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