【專利核准公告】P89004A-低功率可程式化邏輯陣列電路的組合方法「LOW POWER PROGRAMMABLE LOGIC ARRAY ASSEMBLY」(已終止維護)
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專利國別 |
美國 |
發表日期 |
2014-08-14 11:09:36 |
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本校案號 |
P89004A |
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專利名稱 |
低功率可程式化邏輯陣列電路的組合方法「LOW POWER PROGRAMMABLE LOGIC ARRAY ASSEMBLY」 |
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發明人 |
王進賢、張清榮、葉經緯 |
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所屬院 |
工學院 |
提案單位 |
電機工程學系暨研究所 |
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類型 |
發明 |
專利權人 |
國立中正大學 |
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申請號 |
09/932,392 |
申請日期 |
2001-08-17 |
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公開號 |
尚未公開
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公開日期 |
尚未公開
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證書號 |
US 6,433,577 B1 |
核准日期 |
2002-08-13 |
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國際分類號 |
H03K-019/177(2006.01) |
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專利權期間 |
2001.08.17~2021.08.16 |
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專利摘要 |
An assembling method for a low-power programmable logic array circuit. The assembling method is capable of reducing delays and unnecessary power consumption. According to the low potential power loss when the dynamic gates in the AND-plane and the OR-plane output a low potential, the high potential power loss when the dynamic gates in the AND-plane and the OR-plane output a high potential and the probability of the dynamic gates outputting a high potential, a selection between new dynamic logic circuit and conventional dynamic circuit is carried out. The conventional dynamic circuit in the AND-plane refers to a conventional dynamic circuit whereas the conventional dynamic circuit in the OR-plane refers to a conventional footless dynamic circuit |
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圖示 |
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