【可授權專利公告】P104024A-時序錯誤偵測與修正之裝置及其常態時序設計方法「DEVICE FOR DETECTING AND CORRECTING TIMING ERROR AND METHOD FOR DESIGNING TYPICAL-CASE TIMING USING THE SAME」

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專利國別 |
美國 |
發表日期 |
2017-12-12 14:02:43 |
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本校案號 |
P104024A |
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專利名稱 |
時序錯誤偵測與修正之裝置及其常態時序設計方法「DEVICE FOR DETECTING AND CORRECTING TIMING ERROR AND METHOD FOR DESIGNING TYPICAL-CASE TIMING USING THE SAME」 |
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發明人 |
林泰吉、王進賢、林泓志、許庭瑜 |
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所屬院 |
工學院 |
提案單位 |
晶片系統研究中心 |
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類型 |
發明 |
專利權人 |
國立中正大學 |
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申請號 |
15/212,698 |
申請日期 |
2016-07-18 |
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公開號 |
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公開日期 |
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證書號 |
US 9,755,620 B1 |
核准日期 |
2017-09-05 |
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國際分類號 |
H03K-003/037(2006.01) |
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專利權期間 |
2016.07.18~2036.07.18 |
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專利摘要 |
A device for detecting and correcting timing error and a method for designing typical-case timing using the same is disclosed. The device includes two datapath units connected with first and second multiplexers and two transition detectors. Each datapath unit receives and calculates an input signal to generate a speculation value and a correct value. Then, the speculation value and the correct value are transmitted to the first and second multiplexers and the transition detectors determine whether transition of the outputted speculation value is unstable. If yes, the datapath unit outputting the speculation value is stalled for a period of time for correction, whereby the second multiplexer outputs the correct value. If no, the datapath unit outputs the speculation value, then the present invention uses the undertaken timing as a setting specification to complete a circuit design. The present invention can improve system efficiency and power of the whole circuit. |
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圖示 |
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