專利國別

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發表日期

2012-06-22 09:36:21

專利讓與

一、依據本校第261次智慧財產權審議委員會辦理。

二、公告日：2018年05月02日（星期三）。

三、公告讓與期間：自公告日起3個月。

四、敬請有興趣辦理受讓之廠商，或對受讓申請程序有任何疑問者，聯繫研發處技術推廣中心洽談，電話：05-2720411轉16501、16504。

本校案號

P93016A

專利名稱

單一低電壓電源金氧半正反器及其控制方法「FLIP-FLOP IMPLEMENTED WITH METAL-OXIDE SEMICONDUCTORS USING A SINGLE LOW-VOLTAGE POWER SUPPLY AND CONTROL METHOD THEREOF」

發明人

王進賢、李鴻瑜

所屬院

工學院

提案單位

電機工程學系暨研究所

類型

發明

專利權人

國立中正大學

申請號

11/211,666

申請日期

2005-08-26

公開號

US 2007-0046352 A1

公開日期

2007-03-01

證書號

US 7,224,197 B2

核准日期

2007-05-29

國際分類號

H03K-003/289(2006.01)

專利權期間

2005.08.26~2025.08.26(延長105天至2025.12.09)

專利摘要

The present invention discloses a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof, wherein an external control signal is input to a power switch in order to turn on the power switch for an active mode or to turn off the power switch for a sleep mode and inputting an external sleep control signal; the power switch is used to control a combinational circuit to enter into the active or the sleep mode, and the combinational circuit is connected to a virtual power supply; an internal clock signal is separately input to a master stage and a slave stage of the flip-flop, and whether to enter into the sleep mode or the active mode is determined by the voltage level of the internal clock signal. In the present invention, all the logic gates of the combinational circuit are formed of low-threshold CMOS"s, which enables the present invention to maintain a given operation speed at a lower voltage. The flip-flop of the present invention is formed of both low-threshold and high-threshold elements, whereby not only the operation speed can be maintained but also the leakage current can be suppressed spontaneously, and further, the wake-up time can be shortened.

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