專利國別

  美國   

發表日期

2022-10-19 11:32:47

專利讓與

一、依據經濟部科學技術研究發展成果歸屬及運用辦法第22條規定辦理。

二、依據本校第355次智慧財產權審議委員會辦理。

三、公告日：2022年10月19日(星期三)。

四、讓與公告期間：自公告日起3個月。

五、敬請有興趣辦理受讓之廠商，或對受讓申請程序有任何疑問者，聯繫研發處技術推廣中心洽談，電話：05-2720411轉16501、16505。

本校案號

P100057A

專利名稱

可配置化階層式無逗式里德所羅門解碼電路及方法「CONFIGURABLE HIERARCHICAL COMMA-FREE REED-SOLOMON DECODING CIRCUIT AND METHOD THEREOF」

發明人

朱元三、陳奕任、黃佳盈、李奇芳

所屬院

工學院

提案單位

晶片系統研究中心

類型

發明

專利權人

國立中正大學

申請號

12/423,897

申請日期

2009-04-15

公開號

US 2010/0146373 A1

公開日期

2010-01-10

證書號

US 8,166,377 B2

核准日期

2012-04-24

國際分類號

H03M-013/00(2006.01)

專利權期間

2009.04.15~2029.04.15(延長647天至2031.01.22)

專利摘要

The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirement.

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