專利國別

  美國   

發表日期

2013-09-24 12:01:09

本校案號

P100031A

專利名稱

全數位時脈校正電路及其方法「FULL-DIGITAL CLOCK CORRECTION CIRCUIT AND METHOD THEREOF」

發明人

鍾菁哲、沈頌恩

所屬院

工學院

提案單位

資訊工程學系暨研究所

類型

發明

專利權人

國立中正大學

申請號

13/453,094

申請日期

2012-04-23

公開號

US 2013-0187693 A1

公開日期

2012.01.20

證書號

US 8,487,680 B1

核准日期

2013-07-16

國際分類號

H03K-003/017(2006.01)

專利權期間

2012.04.23~2032.04.23

專利摘要

The present invention provides a full-digital clock duty by cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correction module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-adjusted. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse width of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

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