【專利核准公告】P109007US-可變延遲計算裝置「 VARIABLE-LATENCY DEVICE TO REDUCE SENSE ERROR IN MULTI-LEVEL MULTI-BIT SENSING SCHEME」
|
專利國別 |
美國 |
發表日期 |
2022-09-28 15:45:41 |
|
本校案號 |
P109007US |
||
|
專利名稱 |
可變延遲計算裝置「 VARIABLE-LATENCY DEVICE TO REDUCE SENSE ERROR IN MULTI-LEVEL MULTI-BIT SENSING SCHEME」 |
||
|
發明人 |
林泰吉、胡祐嘉、丁意軒、王進賢 |
||
|
所屬院 |
工學院 |
提案單位 |
晶片系統研究中心 |
|
類型 |
發明 |
專利權 |
國立中正大學 |
|
申請號 |
17/152,919 |
申請日期 |
2021.01.20 |
|
公開號 |
US11309016B1 |
公開日期 |
2022.04.19 |
|
證書號 |
US11,309,016B1 |
核准日期 |
2022.04.19 |
|
國際分類號 |
G11C 7/12(2006.01); G06F 3/06(2006.01); G06F 7/544(2006.01); G06F 16/22(2019.01); G11C 11/4076(2006.01); G11C 11/408(2006.01); G11C 11/4091(2006.01); G11C 11/4094(2006.01); G11C 11/4097(2006.01) |
||
|
專利權期間 |
2021.01.20~2041.01.20 |
||
|
專利摘要 |
A variable-latency computing device includes a computing module, enabling units, a storage operation unit, and a detecting controller. The enabling units are divided into at least two groups. The storage operation unit includes word lines and bit lines. The enabling units enable the word line. The storage operation unit accumulates the data values corresponding to the bit lines and the enabled word line, thereby computing first accumulation values. The detecting controller controls the computing module to stop receiving the first accumulation values when the sum of the first accumulation values is higher than a threshold value and takes turns to turn off the at least two groups. The storage operation unit computes second accumulation values during different periods. The computing module receives and computes the second accumulation values corresponding to the at least two groups, so as to generate a computation value. |
||
|
圖示 |
|||
